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TDA9901
Wideband differential digital controlled variable gain amplifier
Rev. 04 -- 14 August 2008 Product data sheet
1. General description
The TDA9901 is a wideband, low-noise amplifier with differential inputs and outputs. The TDA9901 incorporates an Automatic Gain Control (AGC) function with digital control. The TDA9901 is optimized for fast switching between different gain settings, preserving small phase and amplitude error. The TDA9901 presents an excellent combination of low noise and good linearity for a wide input frequency range. The TDA9901 is optimized for processing Input Frequency (IF) signals. It is also suited for many other applications as a general purpose digitally controlled variable gain amplifier. The TDA9901 is able to operate from 4.75 V to 5.25 V supply for the analog part and from 3.0 V to 5.25 V for the digital part.
2. Features
I I I I I I I I I I I I I 130 MHz, -3 dB small signal bandwidth Digitally controlled gain Transistor-Transistor Logic (TTL) and CMOS compatible digital inputs (3.3 V or 5 V) TTL single-ended or differential clock input with Positive Emitter-Coupled Logic (PECL) compatibility 24 dB gain control range Four steps of 6 dB plus 6 dB fixed gain 30 dB gain maximum High impedance differential inputs Low impedance differential inputs High power supply rejection 125 nV/Hz output voltage noise density at 30 dB gain Fast gain settling Dual control modes: transparent or latched
3. Applications
I I I I I I Linear AGC systems Wireless infrastructure Fixed network Instrumentation Multipurpose amplifier Driver for differential ADCs (e.g. ADC1206S040/055/070 and ADC1006055/070)
NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
4. Quick reference data
Table 1. Quick reference data VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = -40 C to +85 C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 C unless otherwise specified [1]. Symbol Parameter VDDA VDDD IDDA IDDD Gmin analog supply voltage digital supply voltage analog supply current digital supply current minimum gain DC input: Tamb = 25 C all temperatures Gmax maximum gain DC input: Tamb = 25 C all temperatures B_3dB Ptot
[1]
Conditions
Min 4.75 3.0 5.78 5.7 29.9 29.3 110 -
Typ 5.0 3.3 30 3.0 6.11 6.11 30.5 30.5 130 160
Max 5.25 5.25 36 5.0 6.40 6.46 30.9 31.5 216
Unit V V mA mA dB dB dB dB MHz mW
-3 dB bandwidth total power dissipation
Vo(dif)(p-p) = 0.125 V; Tamb = 25 C
Due to on-chip regulator behavior a warm-up time of 1 minute (typical) is recommended for optimal performance.
5. Ordering information
Table 2. Ordering information Package Name TDA9901TS SSOP20 Description plastic shrink small outline package; 20 leads; body width 4.4 mm Version SOT266-1 Type number
TDA9901_4
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Product data sheet
Rev. 04 -- 14 August 2008
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
6. Block diagram
VDDD TE GRAY2 GRAY1 GRAY0 CLK CLKN VSSD
18
2
19
20
1
3
4
17
DECODER
LATCHES
TDA9901
IN INN 6 7 0, 6, 12, 18 or 24 dB 15 14 OUT OUTN
CMVGA
5
REFERENCE GENERATOR 11
REFERENCE GENERATOR 8, 9, 10, 13 12
16
CMADC
014aaa474
VDDA
n.c.
VSSA
Fig 1. Block diagram
TDA9901_4
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
7. Pinning information
7.1 Pinning
GRAY0 TE CLK CLKN CMVGA IN INN n.c. n.c.
1 2 3 4 5 6 7 8 9
20 GRAY1 19 GRAY2 18 VDDD 17 VSSD 16 CMADC
TDA9901 TS
15 OUT 14 OUTN 13 n.c. 12 VSSA 11 VDDA
n.c. 10
014aaa475
Fig 2. Pin configuration
7.2 Pin description
Table 3. Symbol GRAY0 TE CLK CLKN CMVGA IN INN n.c. n.c. n.c. VDDA VSSA n.c. OUTN OUT CMADC VSSD Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description digital control signal bit 0 input (Least Significant Bit (LSB)) transparent enable input clock input for gain control setting inverting clock input for gain control setting (active LOW) regulator output common mode VGA input non-inverting analog input inverting analog input (active LOW) not connected not connected not connected analog supply voltage analog ground not connected inverting analog output (active LOW) non-inverting analog output regulator output common mode ADC input digital ground
TDA9901_4
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Product data sheet
Rev. 04 -- 14 August 2008
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
Pin description ...continued Pin 18 19 20 Description digital supply voltage digital control signal bit 2 input (Most Significant Bit (MSB)) digital control signal bit 1 input
Table 3. Symbol VDDD GRAY2 GRAY1
8. Functional description
The TDA9901 provides a digitally controlled variable gain function for high-frequency applications. The TDA9901 can be operated in two different modes, depending on the value at pin TE. When TE is at logic 1, the gain can be instantly controlled when the clock signal is HIGH (transparent mode). The gain is fixed during the LOW period of the clock. When TE is at logic 0 the gain of the TDA9901 is changed at the rising edge of the clock signal.
9. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDD VDD VI IO Tstg Tamb Tj Parameter analog supply voltage digital supply voltage supply voltage difference input voltage output current storage temperature ambient temperature junction temperature VDDA - VDDD Conditions Min -0.3 -0.3 -0.1 -0.3 -55 -40 Max +7.0 +7.0 +4.0 +7.0 10 +150 +85 150 Unit V V V V mA C C C
10. Thermal characteristics
Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Value 120 Unit K/W
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
11. Characteristics
Table 6. Characteristics VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = -40 C to +85 C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 C unless otherwise specified [1]. Symbol Supplies VDDA VDDD VDD IDDA IDDD Ptot B_3dB td(grp) td(grp) ts analog supply voltage digital supply voltage supply voltage difference analog supply current digital supply current total power dissipation -3 dB bandwidth group delay time group delay time variation settling time Vo(dif)(p-p) = 0.125 V; Tamb = 25 C up to fi = 20 MHz; minimum gain; Tamb = 25 C 6 dB gain step; Tamb = 25 C 10 % to 90 % maximum output transition; CL(max) = 5 pF on each output; Tamb = 25 C DC input: Tamb = 25 C all temperatures Gmin minimum gain DC input: Tamb = 25 C all temperatures Gmax maximum gain DC input: Tamb = 25 C all temperatures G/T G/VCC Vi(offset) NF gain variation with temperature gain variation with supply voltage offset input voltage variation noise figure minimum gain maximum gain minimum gain 6 dB gain step Rs = 100 ; fi = 20 MHz minimum gain maximum gain 29.1 9.9 dB dB 29.9 29.3 30.5 30.5 -1.0 -7.5 15 0.8 30.9 31.5 25 dB dB mdB/C mdB/C mdB/V mV 5.78 5.7 6.11 6.11 6.40 6.46 dB dB 5.88 5.6 6.09 6.09 6.28 6.56 dB dB VDDA - VDDD 4.75 3.0 -0.2 110 5.0 3.3 30 3.0 160 130 2.5 5.25 5.25 +2.5 36 5.0 216 300 3.6 V V V mA mA mW MHz ns ps ns Parameter Conditions Min Typ Max Unit
Variable gain amplifier transfer characteristics
Gstep
step of gain
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
Table 6. Characteristics ...continued VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = -40 C to +85 C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 C unless otherwise specified [1]. Symbol Vn(o)(eq) Parameter equivalent output noise voltage Conditions G = 6 dB G = 12 dB G = 18 dB G = 24 dB G = 30 dB PSRR power supply rejection ratio minimum gain; VDDA 0 MHz to 20 MHz 20 MHz to 100 MHz minimum gain; VDDD 0 MHz to 20 MHz 20 MHz to 100 MHz CMRR common mode rejection 0 MHz to 20 MHz ratio 20 MHz to 100 MHz maximum peak-to-peak input voltage common-mode input voltage input current input resistance input capacitance outputs[2] maximum gain minimum gain referenced to VDDA; Tamb = 25 C 2.0 2.0 V V Vi(cm) = 2.7 V minimum gain maximum gain 2.0 10 67 51 75 45 1.0 60.4 2.7 55 VDDA - 1.9 5 dB dB dB dB V mV V A k pF 57 39 dB dB Min Typ 75 82 97 91 124 Max Unit nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz Rs = 100 ; fi = 20 MHz; Tamb = 25 C
Analog inputs Vi(p-p)(max) Vi(cm) Ii Ri Ci Analog
Vo(dif)(p-p)max maximum peak-to-peak differential output voltage VO(cm) VO(cm)/T common-mode output voltage common-mode output voltage variation with temperature single-ended slew rate output resistance output capacitance second harmonic level
VDDA - 2.56 VDDA - 2.42 VDDA - 2.29 V -1.8 mV/C
SRse Ro Co 2H
Vo = Vo(max) fi = 0.5 MHz fi = 4.43 MHz fi = 12.5 MHz fi = 21.4 MHz -
275 15 3
26 -
V/s pF
Variable gain amplifier dynamic performance; CL = 5 pF; RL = 680 ; see Figure 6, 7, 8, 9 and 10 -80 -77 -76 -74 -67 -67 -65 -62 dBc dBc dBc dBc
TDA9901_4
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
Table 6. Characteristics ...continued VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = -40 C to +85 C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 C unless otherwise specified [1]. Symbol 3H Parameter third harmonic level Conditions Vo = Vo(max); Tamb = 25 C fi = 0.5 MHz fi = 4.43 MHz fi = 12.5 MHz fi = 21.4 MHz 3H/T third harmonic level variation with temperature reference voltage output resistance reference output voltage variation with temperature maximum output current output capacitance reference voltage output resistance reference output voltage variation with temperature maximum output current output capacitance hold time set-up time pulse width propagation delay settling time 10 % to 90 % full scale if 6 dB gain change
[3]
Min -
Typ -64 -64 -62 -61 80
Max -60 -59 -58 -57 -
Unit dBc dBc dBc dBc mdB/C
fi = 21.4 MHz
Reference voltage output ADC: pin CMADC Vref Ro Vo(ref)/T referenced to VDDA; Tamb = 25 C Tamb = 25 C VDDA - 1.64 VDDA - 1.45 VDDA - 1.26 V 17 -0.11 26 mV/C
Io(max) Co Vref Ro Vo(ref)/T
referenced to VDDA; Tamb = 25 C Tamb = 25 C
1.0 3
-
mA pF
Reference voltage output VGA: pin CMVGA VDDA - 2.48 VDDA - 2.30 VDDA - 2.17 V 9 1.75 20 mV/C
Io(max) Co th tsu tw tPD ts
2.0 3.8 5.8 -
1.0 3 4.2 2.6
5.9 3.2
mA pF ns ns ns ns ns
Gain switching characteristics (in latched mode); fclk = 52 MHz; Tamb = 25 C; see Figure 3
Gain switching characteristics (in transparent mode); fclk = 52 MHz; Tamb = 25 C; see Figure 4 tPD ts propagation delay settling time 10 % to 90 % full scale if 6 dB gain change
[4]
-
6.7 5.4
9.5 6.9
ns ns
Clock timing input: pins CLK and CLKN (see Figure 3) fclk(max) tw(clk)L tw(clk)H
TDA9901_4
maximum clock frequency LOW clock pulse width HIGH clock pulse width
52 4.0 4.0
Rev. 04 -- 14 August 2008
-
-
MHz ns ns
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
Table 6. Characteristics ...continued VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = -40 C to +85 C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 C unless otherwise specified [1]. Symbol tr tf VIL VIH IIH IIL Ci VIL VIH IIH IIL Ci VIL VIH IIH IIL Ci Vi(dif)(p-p) Parameter rise time fall time LOW-level input voltage HIGH-level input voltage HIGH-level input current LOW-level input current input capacitance LOW-level input voltage HIGH-level input voltage HIGH-level input current LOW-level input current input capacitance LOW-level input voltage HIGH-level input current LOW-level input current input capacitance peak-to-peak differential DC voltage level = 2.5 V input voltage VDDA = 5.0 V
[6] [6] [5] [5]
Conditions
Min 0 2.0 -10 -10 0 2.0 15 -40 3.19 3.83 15 -40 0.1
Typ 4.0 4.0 -
Max 0.8 VDDD +10 +10 3 0.8 VDDD 80 -10 2 3.52 4.12 80 -5 2 2.0
Unit ns ns V V A A pF V V A A pF V V A A pF V
Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2
Clock inputs in TTL mode
Clock inputs in differential mode HIGH-level input voltage VDDA = 5.0 V
[1] [2] [3] [4] [5] [6]
Due to the behavior of the on-chip regulator a warm-up time of 1 minute (typical) is recommended for optimal performance. The analog output voltages are positive with respect to VSSA. In latching mode (pin TE LOW), the gain settling is latched at the rising edge of the clock input. In transparent mode, the gain settling is directly controlled by the input data pattern. The circuit may be used with a single TTL clock on CLK or CLKN. The unused clock pin has to be decoupled to ground with a 100 nF capacitance. There are four modes of operation for the clock inputs in non-TTL mode: a) PECL mode 1: (DC level vary 1 : 1 with VDDA) CLK and CLKN inputs are differential PECL levels. b) PECL mode 2: (DC level vary 1 : 1 with VDDA) CLK input is at PECL level and gain change takes place on the rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLKN decoupled to VSSD via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1 : 1 with VDDA) CLKN input is at PECL level and gain change takes place on the rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLK decoupled to VSSD via a 100 nF capacitor. d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.1 V (p-p) and with a DC level of 2.5 V, the gain change takes place on the rising edge of the clock signal. When driving the CLKN input with the same signal, gain change takes place on the falling edge of the clock signal. NXP Semiconductors recommends decoupling of the CLKN or CLK input to VSSD via a 100 nF capacitor.
TDA9901_4
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Product data sheet
Rev. 04 -- 14 August 2008
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
12. Additional information relating to Table 6
Table 7. State Input coding Gray input data code Pins Gray2, Gray1, Gray0 D2 0 1 2 3 4 other 0 0 0 0 1 D1 0 0 1 1 1 D0 0 1 1 0 0 minimum minimum + 6 minimum + 12 minimum + 18 minimum + 24 minimum + 24 Gain (dB)
tr
tf LOW
CLK
50 % HIGH tw(clk)H tw(clk)L
GRAY0 GRAY1 GRAY2 tsu th gain N gain N + 1
LOW 50 % HIGH
Vo(max) OUT and OUTN 90 % gain N gain N + 1 10 % 0.5 Vo(max) ts tPD 0V
014aaa476
Fig 3.
Latched mode timing diagram
TDA9901_4
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Product data sheet
Rev. 04 -- 14 August 2008
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
GRAY0 GRAY1 GRAY2 gain N gain N + 1 50 %
LOW
HIGH
OUT and OUTN ts tPD
90 % gain N gain N + 1 10 %
Vo(max)
0.5 Vo(max)
0V
014aaa477
Fig 4. Transparent mode timing diagram with CLK HIGH
CMVGA
5
15
OUT
47 nF
Vi
680 C1(1)
42
IN FILTER
100 100
TDA9901TS
6
680
ADC1206S 055 (ADC)
D0...11
sine wave generator
100 nF
INN 7 14
OUTN 47 nF
Vi
C2(1)
43
36 CLK
30 MHz
dB
(2) (3)
014aaa468
(1) C1 and C2 represent the board line capacitance. They represent about 5 pF with the ADC1206S040/055/070 input capacitance. Special care has to be taken to minimize this load in order to have the best dynamic performance. (2) The 2H and 3H of the ADC1206S040/055/070 is lower than that measured on the TDA9901. This measurement method is preferred to conventional methods due to its low contribution to the 2H. (3) The chain measurement shows the harmonic distortion of the TDA9901 as the measurement from ADC1206S040/055/070 is negligible.
Fig 5. Dynamic distortion measurement diagram
TDA9901_4
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
-55 HD (dBc) -65
014aaa469
-55 HD (dBc) -65
(1)
014aaa470
(1)
(2)
-75
-75
(2)
-85 10-1
1
10 f (MHz)
102
-85 10-1
1
10 f (MHz)
102
(1) 3H. (2) 2H. Typical condition; 2 V (p-p) differential output
(1) 3H. (2) 2H. Typical condition; 2 V (p-p) differential output
Fig 6. Harmonic Distortion (HD) as a function of frequency for minimum gain
Fig 7. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 6 dB
-55 HD (dBc)
(1)
014aaa471
-55 HD (dBc)
(1)
014aaa472
-65
-65
(2)
-75
-75
(2)
-85 10-1
1
10 f (MHz)
102
-85 10-1
1
10 f (MHz)
102
(1) 3H. (2) 2H. Typical condition; 2 V (p-p) differential output
(1) 3H. (2) 2H. Typical condition; 2 V (p-p) differential output
Fig 8. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 12 dB
Fig 9. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 18 dB
TDA9901_4
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Product data sheet
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NXP Semiconductors
TDA9901
Wideband differential digital controlled variable gain amplifier
-55 HD (dBc) -65
014aaa473
(1)
-75
(2)
-85 10-1
1
10 f (MHz)
102
(1) 3H. (2) 2H. Typical condition; 2 V (p-p) differential output
Fig 10. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 24 dB
TDA9901_4
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Product data sheet
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TDA9901
Wideband differential digital controlled variable gain amplifier
13. Application information
13.1 Application diagrams
GRAY0 TE CLK CLKN(1)
1 2 3 4 5
20 19 18
GRAY1 GRAY2
100 nF
3.3 V
100 nF 47 F
17 16
100 nF
TDA9901TS
IN
100 100
R1(2) 47 nF
R2(2)
47 F
100 nF
VIN
6
15
47 nF
OUT OUTN n.c.
INN 1:1 n.c. n.c. n.c.
7 8 9 10
14 13 12
100 nF
11 5V
014aaa478
(1) Single-ended clock signal can be applied if required. (2) R1 and R2 should be at least 680 .
Fig 11. Application diagram
13.2 Recommended companion chip
Table 8. Recommended companion chips Description Single 10 bits ADC Single 10 bits ADC Single 12 bits ADC Single 12 bits ADC Single 12 bits ADC Sampling frequency 55 MHz 70 MHz 40 MHz 55 MHz 70 MHz Type number ADC1006S055 ADC1006S070 ADC1206S040 ADC1206S055 ADC1206S070
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Product data sheet
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TDA9901
Wideband differential digital controlled variable gain amplifier
14. Package outline
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
D
E
A X
c y HE vM A
Z
20
11
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
10
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 o 0
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC MO-152 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT266-1 (SSOP20)
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Product data sheet
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TDA9901
Wideband differential digital controlled variable gain amplifier
15. Revision history
Table 9. Revision history Release date 20080814 Data sheet status Product data sheet Change notice Supersedes TDA9901_3 Document ID TDA9901_4 Modifications: TDA9901_3 TDA9901_2 TDA9901_N_1
* *
Correction made to VDD conditions in Table 4. Corrections made to values of td(grp) and Gstep in Table 6. Product specification Product specification Product specification TDA9901_2 TDA9901_N_1 -
20080611 19991008 19980415
TDA9901_4
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Product data sheet
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TDA9901
Wideband differential digital controlled variable gain amplifier
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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TDA9901
Wideband differential digital controlled variable gain amplifier
18. Contents
1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 13.1 13.2 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 10 Application information. . . . . . . . . . . . . . . . . . 14 Application diagrams . . . . . . . . . . . . . . . . . . . 14 Recommended companion chip . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 August 2008 Document identifier: TDA9901_4

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